Skip to main content

Image

Space product assurance

Design, selection, procurement and use of die form monolithic microwave integrated circuits (MMICs)

Foreword

This Standard is one of the series of ECSS Standards intended to be applied together for the management, engineering and product assurance in space projects and applications. ECSS is a cooperative effort of the European Space Agency, national space agencies and European industry associations for the purpose of developing and maintaining common standards. Requirements in this Standard are defined in terms of what shall be accomplished, rather than in terms of how to organize and perform the necessary work. This allows existing organizational structures and methods to be applied where they are effective, and for the structures and methods to evolve as necessary without rewriting the standards.

This Standard has been prepared by the ECSS-Q-ST-60-12C Working Group, reviewed by the ECSS Executive Secretariat and approved by the ECSS Technical Authority.

Disclaimer

ECSS does not provide any warranty whatsoever, whether expressed, implied, or statutory, including, but not limited to, any warranty of merchantability or fitness for a particular purpose or any warranty that the contents of the item are error-free. In no respect shall ECSS incur any liability for any damages, including, but not limited to, direct, indirect, special, or consequential damages arising out of, resulting from, or in any way connected to the use of this Standard, whether or not based upon warranty, business agreement, tort, or otherwise; whether or not injury was sustained by persons or property or otherwise; and whether or not loss was sustained from, or arose out of, the results of, the item, or any services that may be provided by ECSS.

Published by:     ESA Requirements and Standards Division
    ESTEC, ,
    2200 AG Noordwijk
    The
Copyright:     2008 © by the European Space Agency for the members of ECSS

Change log

ECSS-Q-60-12A


25 August 2006


 First issue


ECSS-Q-60-12B



Never issued


ECSS-Q-ST-60-12C


31 July 2008


 Second issue


The following editorial changes have been implemented to comply with the ECSS drafting rules:


Terms and definitions have been divided in clauses 3.1 and 3.2.


For synonymous, the ECSS format have been applied (see 3.2.11-3.2.13).


When descriptive text and requirements were under the same heading, they have been split in two different headings (see e.g. 5.1).


Clarifications to requirements have been presented as NOTES (see e.g. NOTE to 7.1.3).


Each requirement has been given an individual identifier.


Verbal forms have been used consistently, and in conformance with the ECSS drafting rules, and each requirement has been given an individual identifier (see e.g. 4.2).


Requirements in tables have been moved to the body text (see 8.2b, 8.2c and Table 81).


Document requirement definitions in 7.2.1, 7.3.10, 7.3.13, 7.3.14, 9a, 9b and 10.2.4.3 have been moved respectively to Annexes A, B, C, D, E and F.


The following requirements have been reworded for clarity: 7.2.1, 7.2.10d, 7.3.14a, 9c and 10.4.6a.2.


Only documents explicitly called up in requirements have been included in Clause 2 “Normative references”. Only documents explicitly mentioned in the text (other than requirements) have been included in Bibliography. References not explicitly mentioned in the text have been included in informative Annex H “References”.


Introduction

This Standard covers the design, selection, procurement and use of IIIV monolithic microwave integrated circuits (MMICs) for space equipment.

It defines the design activity for the technical (methodology, phases to be followed) and quality (quality assurance, design review) aspects, and, the selection and procurement rules for these components taking into account whether or not the processes have been validated.

Scope

This Standard applies to all types of MMIC (monolithic microwave integrated circuit) based on IIIV compound materials for RF applications (i.e. frequency range ≥ 1 GHz). The requirements for the procurement of components in die form are defined.

It is not within the scope of this Standard to address packaged MMICs and discrete microwave components, these are dealt with in the relevant ESCC specification (ESCC 9010 and ESCC 5010).

This standard may be tailored for the specific characteristic and constraints of a space project in conformance with ECSS-S-ST-00.

Normative references

The following normative documents contain provisions which, through reference in this text, constitute provisions of this ECSS Standard. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on this ECSS Standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references the latest edition of the publication referred to applies.

ECSSS-ST00-01


ECSS system— Glossary of terms


ECSSQST-3011


Space product assurance — Derating - EEE components


ECSSQST-60


Space product assurance Electrical, electronic and electromechanical (EEE) components


ECSSQST-6005


Space product assurance — Generic requirements for hybrids


MILSTD883


Tests methods and procedures for microelectronics


ESCC 20600


Preservation, packaging and despatch of ESCC electronic components


ESCC 24600


Minimum quality management system requirements


ESCC 2049010


Internal visual inspection of monolithic microwave devices


ESCC 2439010


Requirements for capability approval of MMICs


ESCC 9010


Generic specification for MMICs


Terms, definitions and abbreviated terms

Terms from other standards

For the purpose of this document, the terms and definitions given in ECSSSST0001 apply.

For the purpose of this document, the following term from ECSS-Q-ST-60-05 applies:

process identification document

Terms specific to the present document

batch lot
wafers from the same basic raw materials processed as a single set in the manufacturing sequence (diffusion, metallization and passivation process) in a limited and controlled period of time

A unique identifier or code is assigned to a batch lot and to each wafer for processing traceability purposes.

design rules check
control procedure for verifying that design rules have been satisfied

  • 1    Design rules checks are generally issued by the supplier.
  • 2    DRC is performed using software.
    designer
    organization responsible for the design of the MMICs

die lot
set of all dies coming from a single wafer lot

electrical rule check
control procedure for verifying that the electrical rules have been satisfied

Electrical rules are generally issued by the manufacturer.

evaluated process
mature technology that has been successfully submitted to a set of electrical and environmental testing to demonstrate performance and reliability limits

  • 1    ECSSQST-6001 contains a list of evaluated processes.
  • 2    The ESCC 2269010 specification defines the requirements for the evaluation.
    manufacturer
    foundry responsible for the manufacturing of the MMICs

process control monitor
test vehicle used by the supplier to assess the stability of the manufacturing process by means of controls conducted during a wafer production cycle

The PCM is repeated a number of times (depending on the manufacturers) on each wafer lot. The measurements taken during the PCM are used to accept or reject the wafer according to the relevant DC and RF criteria defined in the design manual.

production lot
device types manufactured from the same basic raw materials on the same production line, processed under the same manufacturing techniques and controls using the same type of equipment

A production lot may be composed of one or many batch lots.

qualified process
process that has been successfully submitted to a formal qualification testing

The ESCC 20100 specification defines the requirements for the qualification.

reticule
group of circuit layouts (MMIC, TCV, DEC, PCM) defined by design at the mask level, for duplication over the entire wafer during the MMIC manufacturing

statistical process control
tool to control the quality and the stability of the technological process

SPC is implemented by measuring key parameters during the different manufacturing steps and their analysis using appropriate methods.

tile
See reticule

user
entity responsible for the integration of the MMICs at upper level

Example: MMICs are integrated by users into, for example, modules, hybrids, piece of equipment.

validated design
design that is successfully submitted to application approval testing and an MMIC user LAT test

validated process
process that is evaluated or qualified

wafer lot
wafers manufactured from one or more batch lots

Depending on the maturity of the process a wafer lot is defined as follows:
  • Case 1 (non­evaluated or qualified process): a wafer lot is a single wafer.
  • Case 2 (evaluated or qualified process and new MMIC design): a wafer lot is one batch lot.
  • Case 3 (mature process and recurrent MMIC design): a wafer lot is considered to be a production lot of 4 batches manufactured within a 3 month period.

Abbreviated terms

For the purpose of this standard, the abbreviated terms of ECSS-S-ST-00-01 and the following apply:

Abbreviation


Meaning


AQL


acceptance quality level


CTA


circuit type approval


DEC


dynamic evaluation circuit


DRC


design rules check


ERC


electrical rule check


HTRB


high­temperature reverse bias


LAT


lot acceptance test


LTRB


low­temperature reverse bias


MMIC


monolithic microwave integrated circuit


PAD


part approval document


PCM


process control monitor


PID


process identification document


RGA


residual gas analysis


SAM


scanning acoustic microscopy


SEM


scanning electron microscope


SEU


single event upset


SPC


statistical process control


TCV


technological characterization vehicle


WAT


wafer acceptance testing


General requirements

Overview

This Clause defines the requirements for die MMIC procurement. It completes the user LAT requirements for MMIC die lot procurement as defined in ECSSQST-6005.

The responsibilities of the participants (e.g. designer, manufacturer or end­user) are given from the prototype phase to the delivery of the dies for flight model hybrid manufacturing.

Flight model MMIC dies lots procurement

The following steps involved in procuring MMICs for Space applications shall be followed:

  • Process selection, in conformance with clause 5.
  • Allocation of responsibilities, in conformance with clause 6.
  • MMIC design, in conformance with clause 7.
  • Application approval, in conformance with clause 8
  • Procurement and LAT specifications, in conformance with clause 9.
  • Die form procurement sequences, in conformance with clause 10. The requirements for the qualification and procurement of MMIC packaged devices given in ESCC 9010 shall apply.

Minimum quality requirements

The requirements for processing, production control and clean room conditions defined in ESCC 24600 shall apply.
The manufacturer shall implement and maintain a product quality programme, to ensure that reliability and quality is maintained throughout all the phases of manufacturing and testing in conformance with the requirements in ECSSQST-60.

Selection

General

Overview

During the selection of the manufacturing process by the entity in charge of the procurement, components are assessed for their conformance to the requirements on reliability, application and environmental resistance as defined for the project.

Requirements

The selection of a foundry shall take into account the maturity of the technology, the validation status and the qualification domain as defined in ESCC 2439010.
The MMIC design shall be analysed and validated in terms of application domain compared to the qualification domain and space application requirements.

The qualification domain is documented in terms of the following boundaries with respect to any potential failure mode identified on the process:
  • The physical design and procedures that are closely related to the manufacturing process (no major process change identified since the evaluation testing).
  • The electrical design in term of extreme limits (thermal, DC and RF parameters).
  • Function (e.g. oscillator, gain block), and application (e.g. small signal, pulsed, high drive).
  • The performances, the reliability figures, and the environmental resistance.

Process selection

The selection of the foundry, and the manufacturing process, shall be justified by the supplier, and approved by the customer.
The agreement shall be based on the specific application for which the MMIC is designed and on further considerations such as:

  • The maturity of the process.

E.g. large volume production or experimental technology.
  • The adequacy of the application to the electrical foundry manual, considering, as a minimum, the following items:
    • Equivalent circuits based on measurement results for all passive elements, including lumped and distributed components, in a format compatible for use with standard circuit simulators.

E.g. transmission lines and discontinuities.

 
* Small signal (at various bias points) and large signal models of active components based on measurement results, in a format compatible for use with standard circuit simulators.

Example of such components are transistors, but also Schottky and varactor diodes.

 
* Availability of standard components

E.g. lange couplers.

 
* Layout libraries, in a format compatible for use with standard circuit simulators.  
* Thermal, reliability, process variation design parameters.  
* Space evaluation or qualification status including the results of reliability evaluations performed by the foundry.

A foundry manual for each process used, shall be delivered to the customer (provided the current issue is not already available) prior to the design phase.
The MMIC specifications (satisfying the overall equipment requirements) shall be established within the technical limits of the MMIC process used, and be finalised following an iterative process.

Models, and design tools

Only approved models (fully experimentally verified and included in the foundry manual) and design tools shall be used to design all the passive and active (linear and non­linear) elements.
Any non­standard models and design tools shall be justified, and approved by the customer.

Responsibilities

There are two modes for developing and procuring MMICs:

“Foundry” mode: the customer designs the MMIC and is entirely responsible for the design, and the supplier (or manufacturer) only guarantees the technology.

“Catalogue” mode: the supplier designs the MMIC and is entirely responsible for both the design and the technology, except for issues related to incompatibility between the MMIC and the environment in the customer application.

Table 61 summarizes the responsibilities of the supplier and the customer.

Table 61: Customer and supplier responsibilities for the “foundry” and “catalogue” modes

Description


Reference


Responsibility


supplier


customer


Process selection


clause 5


X


X


Design model validated and design tasks conducted


clause 7.2



X


Design reviews


clause 7.3


X


X


Procurement specification





    for MMIC chip procurement under manufacturer and customer shared responsibility


clause 7.3.14


X



    for LAT under customer responsibility),


clause 9



X


Application approval


clauses 8and 10.4.5



X


Procurement activity including:


clause 10




    wafer screening and WAT


clause 10.2.4


X



    dies incoming control


clause 10.3



X


    LAT


clauses 10.4.2, 10.4.3 and 10.4.4



X


    DPA


clause 10.4.6



X


    Failure analysis


clause 10.5



X


MMIC design

Principles of MMIC design

Overview

In this Clause the steps in the design phases and the responsibilities of the designer in the development of the prototype MMICs are defined.

This Clause does not apply to catalogue MMICs already designed for which the supplier guarantees the microwave performances.

General

The synergies between the specific application for which the MMIC is designed and other application areas shall be investigated for possible utilization.

Example of other application areas are: commercial, professional, and military applications.

If the supplier is developing, or has already developed, for another application, an MMIC having a similar functionality to that required by the customer, this MMIC may be considered as a starting point for the new design.

Number of design iterations

The decision to proceed with a second design and manufacturing iteration (redesign) shall be made, for each MMIC, based on the conformance of the electrical design specification and the electrical measurements of the first iteration.
Additional iterations shall be carried out until sufficient margins can be demonstrated.

A design iteration consists of circuit development, simulation, fabrication and measurement.

Design trade­offs

A design trade­off shall be performed including, as a minimum, the following:

  • circuit principles and heritage circuit topology and dependability;
  • gain and compression distribution inside the circuit;
  • overall electrical performance;
  • testability;
  • radiation;
  • assembly;
  • integration;
  • cost effectiveness of the packaging.

Design tasks

Electrical design specification

Prior to any design, the customer shall develop an electrical design specification of the electrical performances for the application in conformance with Annex A.

Design variations

Several design variations for circuit architecture shall be implemented when the critical characteristics of the circuit are such that multiple variations on a design iteration maximise the probability of first­pass success.
The differences between the variations should be such that the probability of success of at least one of the variations is maximized.
Test structures of the most sensitive and critical passive and active circuit elements or sub­parts may be included in the design iteration to increase the diagnostic capabilities.

Parasitic effects

Parasitic effects shall be considered in all the designs and simulated with appropriate (e.g. electromagnetic) design tools.

Examples include the effect of transmission line discontinuities (especially for unusual geometry and for those elements having a very critical influence on overall performance), on­die coupling, interconnections (e.g. bonding wires, external capacitors, impedance of interconnected circuits), assembly, and packaging.

The simulation specified in requirement 7.2.3a may be complemented with experimental data from circuits having a similar layout and characteristics.
If the confidence in a selected structure or component simulation is not sufficient, measures shall be taken to avoid this structure in the design, whenever possible, or the design modified to reduce the criticality of this structure.

Transient simulation

Transient simulations shall be made when circuits operate in pulse conditions.
Simulated results shall be derived for parameters such as, turn on and off times, variations versus pulse length and pulse repetition frequency.
Requirements 7.2.4a and 7.2.4b shall also be applied to oscillators for determining, for example, the build up time.

Thermal analysis

The maximum channel (or junction) temperature shall be computed for the maximum equipment base­plate temperature (operating temperature range).
Measures shall be taken to minimise the temperature by selecting the appropriate size or combination of active devices, their location on the die, and the mounting techniques

E.g. eutectic attachment versus epoxy attachment.

The effects and characteristics of the packages on the circuits shall be analysed.

E.g. power dissipation.

Sensitivity to temperature, process variation and supply voltages

The sensitivity to temperature, process variation and supply voltages shall be simulated using foundry data or measured data from test components.
Yield analysis and estimates based on the design book data shall be carried out to ensure that the circuit operates as specified in the wafer­acceptance criteria (both RF and DC parameters), and that it can withstand uncertainties such as, the accuracy of electrical model parameters and variations.

This includes the choice of, for example, optimum topologies, components, sizes, design centring, worst­case analysis, yield analysis and yield estimate.

The analysis shall be carried out for all parameters subjected to process variations and include, whenever possible, correlations between the different elements that cause variations.
When delivered by the foundry, SPC data should be used.

Design testability

Ground­source­ground pads with the standard pitch defined in the design book, shall be included for all RF ports.
For specific cases, alternative pad arrangements (e.g. G­S or S+ S­ pads) may be used after justification is provided (for example, a significant area reduction effect on the die).
DC pads should be positioned orthogonally to the RF pads.
For critical cases and at higher frequencies, an on­wafer calibration standard can be inserted in the tile.

E.g. to remove uncertainties related to substrate thickness variation.

Design stability analysis

Design stability analysis shall be carried out from the DC to the maximum frequency of the active devices used.
The analysis specified in requirement 7.2.8a (e.g. using  factor or both K and B1 factors) shall be complemented by an internal multi­loop analysis to exclude any possibility of oscillations of the odd­mode type.
For a cascaded structure, as a minimum, the stability of each block shall be checked individually.
The analysis specified in requirement 7.2.8a shall also include the effect of feedback paths caused by the following:

  • the biasing elements (on and off­die);
  • the final packaging;
  • the effects of process variations, temperature, and slight changes of biasing conditions. Circuit stability during on­wafer characterization shall be addressed.

Maximum rating and robustness

The designer shall apply and verify the maximum rating specified by the manufacturer.
The designer shall apply the additional derating in conformance to ECSSQST-3011 or an equivalent customer specification as long as the customer specification does not relax ECSSQST-3011 requirements.
The maximum current densities and maximum voltages shall be evaluated in the whole circuit both at DC and RF operating conditions.

E.g. multi­carrier signal.

The maximum level of stress under RF conditions in any device shall be limited to conditions equivalent to those for which the process reliability evaluation is carried out.

Example of these RF conditions are gain compression, and effects of multi­carrier loading.

The circuit topology shall take into account the circuit reliability while maintaining acceptable electrical characteristics.

Example of reliability conditions to take into account are the use of L­parallel, C­series matching networks at input to reduce sensitivity to static discharge, and choice of transmission line size.

The effect of radiation shall be included (if applicable to the process used).
Any new MMIC design shall be analysed with respect to the process reliability figures compatible with the future application.
If the results of the analysis of the design and the application are out of the qualified domain, the customer (or the supplier) shall define a quality or reliability test plan for documenting the shortcomings.

Layout optimization

The die area shall be optimised to improve yield and reduce cost, without compromising on the functional performance of the die and testability.
A hierarchical design should be used.
The circuit layout shall be delivered in GDSII format.
The number of available die sites per tile shall be specified, and the layout of the complete tile shall be delivered (except PCM die).
The location and function of any connecting pads shall be specified and numbered.
Testability considerations shall be taken into account.
Assembly drawing shall be complete and include all other components additional to the MMIC.

E.g. filtering capacitors.

The packaging drawing (if applicable) shall be included.

DRC or ERC

The successful output of the design rules checking (DRC) performed at the foundry shall be demonstrated to show conformance with the foundry layout rules (e.g. no errors detected).
The successful output of the electrical rules checking (ERC) performed at the foundry (if performed) shall be demonstrated to show conformance with the foundry electrical rules

E.g. no errors detected.

For all the points not covered by requirements 7.2.11a and 7.2.11b, the supplier shall demonstrate that the design is made within a domain for which the selected process is fully proven.

E.g. frequency range of applicability of models, biasing ranges.

Design reviews

General

Design and layout review meetings shall be held between the supplier and customer.
The supplier shall manage the participation of persons involved in the design and manufacturing.
When the design is completed, the designer shall send the file to the manufacturer for assembly of the final reticule and performance of the DRC.
The design review shall be organized by the supplier at the manufacturer facilities with persons involved in the design and manufacturing to assess whether the circuits are ready for manufacturing.
In the design review meeting, the requirements in clauses 7.3.2 to 7.3.14 shall be addressed in the given order.

MMIC architecture

The designer shall provide a description of the function(s) and their features.
The manufacturer shall verify that the characteristics are realistic with regard to the domain of the process.

Schematic

The designer shall present the electrical scheme of the circuits.

Simulation results

The designer shall state the software or hardware type used for the design.
The designer shall provide the simulation results demonstrating that the circuit belongs to the functionality domain specified and that the MMIC was designed using, for example, models and cells, specified in the design manual.
Any discrepancy or modification in, for example, the models and cells, shall be clearly identified, and justification and documentation supplied.
The designer shall demonstrate that the electrical models used in the simulations are valid for the specified application domain, including the worst case analyses.

Sensitivity and stability analysis

The designer shall provide the results of the sensitivity analysis.
Variations in the manufacturing process shall be taken into account in the design.
Variations in the environment shall be taken into account by the supplier who shall manage the impact.

For example to forward the sensitivity and stability data to the user.

Derating

The designer shall provide the derating for each passive or active element, calculated from the manufacturer maximum rating.
The derating analysis shall be performed for the worst case of use scenario and conform to the requirements of the ECSSQST-3011.

Layout

The manufacturer shall provide the DRC and ERC results.
If no software is available, the ERC shall be made “manually” on a large­scale drawing with the following:

  • highlight the connection nodes;
  • surround the basic cells;
  • mark the DC and RF paths;
  • measurement of the track dimensions and compare them to the design rules (current density). For the manual ERC, the designer shall provide, for the review and for each circuit, a schematic of the electrical connections.

Tests matrix

The testing matrix, to be performed by the manufacturer at wafer level or at individual die level, shall be provided by the designer.
The manufacturer shall ensure that he has adequate test facilities to perform the tests.

Assembly

The designer shall specify the mounting technique for assembling the MMICs.
The supplier shall verify that the MMIC process is compatible with the intended mounting technique.

Compliance matrix

The supplier shall issue a compliance matrix for custom MMIC designs (check­list) in conformance with Annex B, based on manufacturer and designer data.
The compliance matrix for custom MMIC design shall be available for customer review.

MMIC detail specification

The designer shall provide the preliminary MMIC detail specification of the circuit based on ESCC format (or equivalent).

Development plan

The development plan of the circuit(s) defining the planning of manufacturing and testing shall be agreed upon by the entity in charge of the procurement of the MMIC.
The design review shall be completed and the authorization for manufacturing given when all the items indicated in the conformance matrix and in the development plan are accepted.
If there are nonconformances, the end of the review shall be pronounced when the corrective actions are closed.
All the reviews shall be recorded as minutes of a meeting, written and signed in session.

Design documentation

For the design of an MMIC, a design package document in conformance with Annex C shall be provided to the customer for approval
The MMIC manufacturing shall not commence before the data package document has been approved by the customer.
The supplier shall provide a compliance table between target requirements and simulated results.

MMIC summary design sheet

Once the design of the MMIC is finalised and verified by tests, a summary design sheet shall be prepared by the supplier, in conformance with Annex D, for approval from the entity in charge of the procurement of the MMIC.

Application approval

General

Application approval shall be carried out on each new designed MMIC in order to validate the compatibility between the MMIC and its specified application.
Dedicated test flow and test procedures shall be implemented in conformance with requirements in clause 8.2.
For microwave hybrids, the testing shall be complementary to the circuit type approval (CTA) as described in the ECSSQST-6005.
Additional hybrids shall be made available with the same quality level as for the CTA (minimum EM hybrid quality level).
Deviations and test conditions to this flow shall be justified by the hybrid manufacturer and agreed with the customer through the part approval document (PAD) procedure.

Test flow and test procedures

The test sequence shall be included as part of the hybrid CTA activities in conformance with ECSSQST-6005. Table 81 summarises the test groups and procedures.
The environment test specified in row 7 of Table 81 shall validate the compatibility of the new MMIC design circuits with the package environment.
It shall not be considered to be a duplication of environmental testing specified in row 7 of Table 81 carried out in the context of the hybrid evaluation and qualification activities used for validating the compatibility between the MMIC and hybrid technologies.
Table 81: CTA tests and procedures for testing in sequence D

Test No.


Test


Procedure and conditions


Sample size


Related failure mechanism


1


Thermal


Thermal analysis of the MMIC to identify hot spots or excess temperature during worst­case operations. Thermo­graphic measurement shall be carried out when the thermal analysis has indicated a less than 20 C margin to the maximum rated temperature under worst­case operation.


2


    Acceleration factor of failure mechanisms.


    Thermometallurgical.


    Diffusion effect (gate sinking, ohmic metal diffusion).


2


Electrical



Current density analysis on the MMIC for worst­case operation and comparison with the design book maximum rating.


NA


Electromigration


3



Characterization of MMIC behaviour over temperature range, under DC or RF and continuous or pulse operation (e.g. stability, lagging).


2


Trapping effect


4



RF Stress overdrive. RF step stress at room temperature, 168 h minimum for the last step. Last step stress shall demonstrate a minimum of 4dB margin against worst­case operation including modulation with no drift on DC and RF parameters.


4


    Application related with impact ionization.


    High RF reverse gate current.


    Power slump burn out due to RF.


5


Radiation



Heavy ions: analysis versus mission profile. Heavy ions testing under room temperature reverse bias conditions.


4


    Burn out.


    SEU for digital application.


6



Electron, proton, neutron: applicability to be addressed on a case­by­case basis.


4


Atoms displacement


7


Environment(see 8.2b and 8.2c)


Hydrogen: high­temperature storage test or HTRB under N2/H2 (minimum 5% H2) environment for a minimum of 240 h or equivalent. RGA analysis extended to all elements after test.


6


    H2 poisoning.


    DC parameters drift.


    Sudden Idss drop.


8



Epoxy or other contaminant: DC life test HTRB) at 150 C for a minimum of 240 h or equivalent. Drift recovery under high­temperature storage with leads short­circuited at T=150 C, 168 h. RGA extended to all elements.


6


    Ionic contaminant (epoxy, residue, RF absorbers).


    DC parameters drift.


9



Moisture, LTRB (Tamb < dew point) 168 h under specified humidity environment due to assembly and storage condition or due to additional element in package e.g. RF absorbent. RGA extended to all elements.


6


    Electrical parameters drift.


    Burn­out.


Procurement and LAT specification

A MMIC procurement specification shall be issued by the supplier in conformance with Annex E, and associated with each MMIC.
A MMIC lot acceptance specification for user LAT shall be issued by the supplier in conformance with Annex F.
The MMIC lot acceptance specification for user LAT shall be implemented.

Clause 10 defines the requirements for the MMIC procurement specification and the MMIC lot acceptance specification for user LAT.

If the mounting and wiring processes are different from the user hybrid process, the procured lot shall be validated with respect to the user process by performing an additional LAT or by using the LAT performed at hybrid level providing sufficient confident data are available.

Procurement

General

Overview

This Clause contains the deviations and amendments to ECSSQST-6005, specific to MMIC procurement.

Methodology

The procurement activity shall comprise the following three steps:

Wafer screening and wafer acceptance testing (WAT) (MMIC manufacturer responsibility), in conformance with requirements in clause 10.2.
Dies incoming inspection (hybrid manufacturer responsibility), in conformance with requirements in clause 10.3.
User lot acceptance testing (LAT) (hybrid manufacturer responsibility), in conformance with requirements in clause 10.4.

Wafer screening and WAT

General

Wafer screening and wafer acceptance testing (WAT) shall be the responsibility of the manufacturer.

The test flow and relevant test conditions are described in clauses 10.2.2 to 10.2.6.

Wafer screening and WAT flows

Figure 101 illustrates the sequence of activities for wafer screening and WAT.

Image Figure 101: Wafer screening and WAT

Wafer manufacturing and control

PCM measurements, rules and controls, shall be in conformance with the manufacturer design book requirements.
Wafers shall be accepted, based on PCM specifications, as defined by the manufacturer.
PCM data that is manufacturer proprietary information, can be delivered, if agreed upon by the manufacturer, and user or customer.
DC and RF on­wafer probing shall be performed by the manufacturer prior to the dicing and be used to sort the dies as defined in the procurement specification.
Optional reviews such as a customer source inspection, may be agreed between the user and the manufacturer.
During the optional reviews specified in 10.2.3e, documentation shall be available that includes:

  • materials and in­process controls;
  • lot travellers;
  • PCM acceptance;
  • SPC data review;
  • SEM of specific processing step;
  • production and quality assurance controls;
  • manufacturer visual inspection data documents and reports.

Wafer acceptance test

General

Wafer acceptance testing (WAT) is the responsibility of, and shall be performed by, the manufacturer.
The WAT shall verify that the process and the MMIC designs are compliant to the space grade quality level.
The WAT shall comprise the following:

  • PCM measurements and a check for wafer release according to the manufacturer specification;
  • 100 % DC and RF on wafer probing;
  • 100 % die visual inspection;
  • a manufacturer assembly test (bond pull test and die shear test). On completion of the WAT, the wafers (issued from the same batch) shall be guaranteed and delivered after dicing in die form as specified in the procurement specification.

DC and RF probing

All the MMICs shall be electrically probed for DC and RF, as defined in the procurement specification.
The dies that pass shall be identified and stored with the appropriate packaging and under suitable conditions.

Dicing and 100 % visual inspection

All visual inspection sequences shall be performed according to ESCC 2049010 or MILSTD883, method 2010 condition A or according to standard professional grade (manufacturer or user procedure) if validated by the customer.
100% of the naked die shall be visually inspected after dicing.
A summary sheet of the visual inspection shall be produced by the supplier in conformance with Annex G, and made available to the customer.

Manufacturer assembly test

In order to guarantee the quality of the interface (bonding pad metals and die back face metals), the manufacturer shall implement an assembly test sequence if specified in the procurement specification.
The assembly test sequence shall be performed by sampling rejected dies (assembled using the manufacturer process) from the wafers manufactured, and includes the following:

  • A bond pull test on 10 wires as per MILSTD883 method 2011.No failures allowed.
  • A die shear test on 2 parts as per MILSTD883 method 2019.No failure allowed. If the test sequence performed is based on the user assembly process and in conformance with the user assembly test defined for the incoming inspection, then this test shall not to be repeated by the user when dies are received.
    For requirement 10.2.4.4c, a document shall be issued by the user stating that the assembly process used by the manufacturer is representative of the hybrid process.

Packaging

All deliverable dies shall be packed in conformance with ESCC 20600.
Waffle packs should be used but can attract dust and cause scratching if not handled with care.
Gel packs shall be validated with respect to any contamination or residue after storage.
All packaging shall be opened in a suitable clean room using the appropriate procedure.
Several categories of dies may be delivered (including yield information):

  • good DC or RF and good visual;
  • good DC or RF and bad visual;
  • test structures (TCV, DEC, PCM).

Deliverables

The data package shall comprise the results of the controls described in clauses 10.2.3 to 10.2.5.
If a data package is not delivered, all data shall be retained by the manufacturer for a minimum of 5 years during which time it shall be available to the customer for review, upon request.
The manufacturer data package documentation shall consist of the following:

  • Cover sheet or declaration of conformity, full traceability (including for lot, batch, wafers, dies), purchase order reference, manufacturer’s name and location of manufacturing plant.
  • Certificate of conformity (manufacturer’s name and location of manufacturing plant, date and manufacturer’s QA signature, reference to the generic and detail specification, including issue and date).
  • Wafer acceptance test data and PCM data summary sheet.
  • DC or RF measurement data for every MMIC type and associated yields.
  • QA visual inspection report (front side and back side). In the “foundry” mode, each type of MMIC shall be delivered, with traceability and quantity information written on the packaging, in two categories:
  • ‘‘accept: good dies (DC or RF) and good visual’’,
  • ‘‘reject: good dies (DC or RF) and bad visual’’.

Dies incoming testing

General

Dies incoming testing shall be carried out when a new die lot is received in conformance with Figure 102

See also clause 3.2.4.

The testing shall include the following test sequence:

  • bondability testing;
  • visual inspection;
  • electrical characterization. Testing shall be carried out by the user for every MMIC die lot and prior to the user LAT.

Assembly test

The assembly test shall verify the compatibility between the MMIC process and the hybrid technology.
The mounting process and the type of package used for the tests shall be representative of the processes employed for the FM hybrids by the user.
The mounting process and the type of package used for the tests shall be described in the specifications included in the PID of the user.
Dies rejected during the front side visual inspection issued from the controls can be used to perform the test.
The MMIC selected for the tests shall have, if possible, the maximum via hole density.
Wire pull testing shall be performed according to MILSTD883 method 2011 on 22 wires or on all the wires if less.     No failure allowed.
The shear test on mounted dies shall be according to MILSTD883 method 2019 on 4 dies.     No failure allowed.
Image Figure 102: Dies or die incoming testing

Visual inspection

The user quality assurance inspector shall carry out a visual inspection of the lot on a 100 % basis or on an AQL 1 %.

Electrical characterization

If an electrical characterization test is performed, 2 parts per design shall be assembled on a carrier or in a package similar to the one used for hybrid FM production.

The objective of this optional testing is to select dies lots for specific application requirements, which cannot be characterised on the wafer.

User LAT procurement sequences

General

Overview

The purpose of the LAT performed by the manufacturer is to assess the reliability of the technology (LAT DEC or TCV) and the reliability of the MMIC design (LAT MMIC). The purpose of the LAT performed by the user is to assess the technology and MMIC design, and the compatibility of the MMIC with the assembly process.

Image Figure 103: Acceptance flow for flight model die lots

Depending on the validated process status of the MMIC, the maturity of the design and the application, the acceptance flow for FM dies is defined in three flow test sequences (Figure 103):

Sequence A: This flow applies when process, design and application have already been validated.

Sequence B: This flow is applies when the process is validated and a new design or a new application needs to be validated.

Sequence C: This flow is applies when the MMIC design, application and the process are not validated.

Requirements

From the three sequences A, B and C shown in Figure 103, the severity of acceptance testing shall be specified in order to obtain consistent Space grade quality levels.
Sequence D of Figure 103 is the application approval as defined in clause 8 and shall be performed to validate new designs or new applications.
The user LAT shall be performed using TCV, DEC or MMICs as per Figure 104 in conformance with ESCC 2439010.
Test vehicles shall be mounted in packages that enable tests (maximum junction temperature Tj = 175 C), electrical measurements and inspections to be performed.
For a LAT performed by the user, the assembly processes and the type of package used for TCV, DEC and MMIC mounting shall be representative of the processes defined in the user’s PID.
The number of units that are assembled shall be sufficient to ensure that after screening, the specified number of units as defined in Figure 104 are available.
The screening of the assembled devices shall include the following:

  • visual inspection (if specified);
  • sealing and serialization;
  • hermeticity (if applicable) (fine and gross leak test) as per MILSTD883 method 1014;
  • DC and RF initial electrical measurement at room temperature (including one control device for reproducibility verification) under nominal DC biasing and nominal RF input;
  • DC burn in at Tch = 175 C, for 96 h under nominal biasing condition (no RF);
  • DC and RF final electrical measurement at room temperature (including one control device for reproducibility verification) under nominal DC biasing and nominal RF input.

See clause 9 for requirements on issuing a specification for user LAT.

Image Figure 104: User LAT flow

Sequence A: process, design and application validated

The user LAT sequence A in Figure 104 shall be applied to the procurement of MMICs processed with a validated process in conformance with customer’s requirements and for which the designs have been validated from a reliability point of view by performing application approval testing.
For high­grade level, the sequence A in Figure 104 shall be conducted on DEC or TCV structures only.
The sampling is related to the number of wafers and shall be 3 DEC or TCV per wafer with a total 12 parts per wafer lot and one control device.
A life test shall be performed on the 12 parts assembled using processes defined in the user’s PID and under nominal biasing conditions (no RF) and high temperature, in an oven, in order to achieve a maximum channel temperature of 175 C with a tolerance of 5 C.
The duration of the test shall be 168 hours for high­grade level (failure criteria A=0, R=1).
If epoxy die attach is used:

  • the temperature within the oven shall be a maximum of 130 C with a tolerance of 5 C; and
  • the duration of the life test shall be based on the Arrhenius acceleration factor with Ea=0,6 eV. 100 % final electrical measurements at room temperature and delta calculation shall be made.    No failure allowed.
    A DPA shall be performed on 2 parts as per clause 10.4.6.    No defect allowed.
    Sequence A in Figure 104 is not applicable for low grade level.

Sequence B: process validated and new design or new application

Sequence B in Figure 104 shall be applied to the procurement of MMICs processed with a validated process according to the customer’s requirements and for which the design is new and not validated from a reliability point of view.
For high­grade level, sequence B in Figure 104 shall be conducted on DEC or TCV structures and on MMIC dice assembled using the processes defined in the user’s PID.
The sampling is related to the number of wafers and shall be 3 DEC or TCV per wafer and 3 MMIC (new) per wafer with a total 12 parts per wafer lot and one control device.
A 168 h life test shall be performed as per clauses 10.4.2d and 10.4.2e on 6 parts DEC or TCV structures.
A 240 h life test shall also be performed on 6 MMIC.
If the parts are epoxy die attached, the same restrictions as given in requirement 10.4.2f shall apply and the calculations for the duration of the test shall be based on the same acceleration factor.
100 % final electrical measurement at room temperature and delta calculation shall be made.    No failure allowed.
A DPA shall be performed on 2 parts (either TCV, DEC or MMIC) as per clause 10.4.6.    No defect allowed.
Sequence B is not applicable for low­grade level.

Sequence C: process, design and application not validated

Sequence C in Figure 104 shall be applied to the procurement of MMIC processed with a non­validated process according to the customer’s requirements.
The user LAT shall be considered to be the lot validation.
It shall be performed on MMICs with the modified conditions given in requirements 10.4.4d to 10.4.4j.
For high­grade level, a 1 000 h life test shall be applied on 12 packaged MMIC per wafer lot (assembly process as per user’s PID).
If the parts are epoxy die attached, the same restrictions as given in requirement 10.4.2f shall apply and the calculations for the duration of the test shall be based on the same acceleration factor.
For low grade level, the duration of the life test shall be reduced to 500 h on 6 parts per wafer lot only.
100% final electrical measurement at room temperature and delta calculation shall be made.    No failure allowed.
For both levels, a DPA shall be performed on 2 parts (one before the life test and one after) (either TCV, DEC or MMIC) as per clause 10.4.6.    No defect allowed.
A construction analysis (CA) shall be performed on 3 dice for the first procured lot.
The CA shall include, as a minimum, the following analyses:

  • external visual inspection (MIL STD 883 method 2009);
  • internal visual inspection (MIL STD 883 method 2010);
  • SEM inspection (MIL STD 883 method 2018);
  • identification of bonding pad and back side metals and their thicknesses;
  • passivation material and thickness;
  • die dimension;
  • micro­section showing the gate zone (with dimensions).

Sequence D: application approval testing

When specified, sequence D in Figure 104 shall be applied, prior to the user LAT sequences.
A test plan shall be issued and agreed upon by the customer.
The test plan shall detail the tests to be performed on a defined quantity of CTA as described in ECSSQST-6005 (see Table 2 of clause 8.2).
The test plan shall be documented and some tests may be omitted if the heritages on the technology or on the design are sufficient and demonstrated.
The user shall be responsible for defining the tests to support the reliability tests based on Table 81.
Hybrids or dedicated packaged MMIC (one MMIC per package) can be used to complete this sequence of test.
For requirement 10.4.5f, the packaged parts shall be representative of the production process defined in the PID (assembly and sealing process) and be screened according to the flow defined in Figure 104 and clause 10.4.
Due to the conditions of stress, some tests may be conducted up to and above the failure limits with the purpose of assessing the existing margin due to a specific constraint.
If 10.4.5h is performed, it should be stated in the test plan document.

Destructive physical analysis after user LAT

The following tests shall be performed as part of the DPA:

  • External visual inspection    MILSTD883 Method 2009.8
  • Seal test             MILSTD883 Method 1014    condition A2 condition C
  • Internal visual inspection     ESCC 2409010 or equivalent
  • Bond pull test        MILSTD883 Method 2011 condition D
  • Die shear test            MILSTD883 Method 2019
  • RGA (option)        MILSTD883 Method 1018.2.

Failure criteria and lot failure

A component shall be considered to be failed if one or more of the electrical parameters (DC and RF) exceed the limits defined in Table 4 of the corresponding detail specification.
In the case of a LAT performed by the manufacturer failures due to the assembly of the test structures shall be excluded from the results, and therefore not lead to lot failure.
In the case of a LAT performed by the user, a part shall be considered failed if at least one test does not satisfy the limits defined in the specification associated to the process.
Any relevant failures (see requirement 10.5f) observed in assembly tests shall be included in a nonconformance sheet and the problem subjected to a review.
The customer shall be informed of the nonconformance and decide when it can be closed.
A failure shall be considered a relevant failure if only address a problem at die level

For example: bond pull failure criteria at wire neck is not considered as a defect from the die point of view.

During user LAT, if the number of components failed during assembly or screening exceeds 10% of the components submitted to these tests and associated electrical measurements, the lot shall be considered as failed.
In the case of requirement 10.5g the lot shall be treated using the nonconformance procedure.
Parts failed during the LAT screening may be replaced by new assembled and re­screened parts in order to make up the quantity for the life test sequence.
A component shall be counted as failed if one or more electrical parameters (DC and RF) exceed the limits defined in Table 4 of the corresponding detail specification.

ANNEX(normative)MMIC electrical design specification - DRD

DRD identification

Requirement identification and source document

This DRD is called from ECSS-Q-ST-60-12, requirement 7.2.1a.

Purpose and objective

The MMIC electrical design specification is the baseline for the design and for the acceptance of the MMIC.

Expected response

Scope and content

The MMIC electrical design specification shall contain, as a minimum, the following:

  • electrical performances and application,
  • die dimension,
  • in and out interfaces.

Special remarks

None.

ANNEX(normative)Compliance matrix for custom MMIC design - DRD

DRD identification

Requirement identification and source document

This DRD is called from ECSS-Q-ST-60-12, requirement 7.3.10a.

Purpose and objective

The purpose of the compliance matrix for custom MMIC design is to summarize the status of the compliance with respect to the specification of the business agreement.

Expected response

Scope and content

The compliance matrix shall summarise the following:

  • The function description and associated main characteristics.
  • The software or hardware used for the design.
  • Verification that the circuit belongs to the specified functional domain and is designed using, for example, the models and cells, described in the design manual. If not, an extension of the qualification domain shall be provided.
  • The results of the sensitivity and stability analyses.
  • The derating of the elementary parts.
  • The DRC results.
  • The ERC results.
  • Verification from the manufacturer that he can perform the set of tests specified by the designer for the wafer or dies release.

Special remarks

The existence of the compliance matrix shall be indicated in the PAD sheet.

ANNEX(normative)Design package document - DRD

DRD identification

Requirement identification and source document

This DRD is called from ECSS-Q-ST-60-12, requirement 7.3.13a.

Purpose and objective

The MMIC design data package document is the set of configured documents related to the design.

Expected response

Scope and content

The design package document shall include the following:

  • Description of functionality and any functional blocks.
  • List of the major critical items in the circuit design and the trade­offs performed.
  • Schematic diagrams.
  • Linear simulation including out­of­band response.
  • Noise analysis, including phase noise (if applicable to the specific circuit).
  • Non­linear simulation, steady state (if applicable to the specific circuit).
  • Transient simulation.
  • Electromagnetic analysis (if applicable to the circuit: this depends on).

For example, the frequency of operation, sensitivity of the circuit, density on the die, thickness of the substrate, type of transmission lines used, similarity with already produced die.
  • DC analysis (if applicable to the circuit),

For example, for non­linear circuits or circuits using DC coupled active elements.
  • Tolerance analysis, stability analysis, thermal analysis, reliability analysis.
  • Layout.
  • DRC or ERC.
  • On­wafer testing (when performed).
  • Cost analysis budgetary cost estimates for production runs of the MMIC designed, including in the case of circuits to be produced in large quantities, a detail cost estimates.
  • Test plan or procedures (including the calibration approach and accuracy).
  • On­wafer and test­jig measurements (including test­jig mechanical and electrical characteristics).

Special remarks

None.

ANNEX(normative)MMIC summary design sheet - DRD

DRD identification

Requirement identification and source document

This DRD is called from ECSS-Q-ST-60-12, requirement 7.3.14a.

Purpose and objective

The MMIC summary design sheet is the set of data characterizing in short the MMIC.

Expected response

Scope and content

The MMIC summary design sheet shall include the following:

  • Name of the circuit.
  • Function.
  • Electrical diagram.
  • Main performance characteristics.
  • Compliance table between target and simulated performance.
  • Name of the final GDSII file.
  • Layout drawing (with dimensions and identification of each connection pad position and function).
  • Foundry process used.
  • Assembly drawing (including external components needed).
  • List of nominal biasing and control voltages or currents, and total power consumption.
  • List of nominal RF signals to be applied or measured.
  • Photograph (in colour and details).

Special remarks

None.

ANNEX(normative)MMIC procurement specification - DRD

DRD identification

Requirement identification and source document

This DRD is called from ECSS-Q-ST-60-12, requirement 9a.

Purpose and objective

The MMIC procurement specification is a support for the acceptance of the MMIC.

Expected response

Scope and content

The MMIC procurement specification shall include, as a minimum, the following:

  • The physical description of the tile and all associated die (name, dimensions, cells).
  • The electrical test plan (DC biasing, RF input conditions) for on­wafer probing.
  • All parameter specification limits to be applied for die sort.
  • Packaging definition.
  • Quality level of visual inspection for die delivered.

Special remarks

The MMIC procurement specification may be merged with the MMIC lot acceptance specification for user LAT (see Annex F) on completion of all testing by the manufacturer and user for the finalization of the MMIC detail specification.

ANNEX(normative)MMIC lot acceptance specification for user LAT - DRD

DRD identification

Requirement identification and source document

This DRD is called up from ECSS-Q-ST-60-12, requirement 9b.

Purpose and objective

The MMIC lot acceptance specification for user LAT is a support for the acceptance of the MMIC.

Expected response

Scope and content

The MMIC lot acceptance specification for user LAT shall contain, as a minimum, the following:

  • Die reference submitted to user LAT (using either a TCV, a DEC or an MMIC).
  • The description of the package to be used for the mounting with lead identification.
  • The description of the mounting and wiring processes.
  • Table 1: maximum ratings. This table shall include the limiting electrical, mechanical and thermal parameters.
  • Table 2: electrical measurements at ambient temperature with static and dynamic parameters.
  • Table 3: electrical measurements at high and low temperatures.
  • Table 4: parameter drifts. This table shows the electrical parameters before and after burn­in with the maximum drift allowed.
  • Table 5: burn in conditions. This table shows the oven temperature and power applied.
  • Table 6: electrical measurements after endurance tests. This table shows the parameters measured and the minimum and maximum values tolerated following the life test at the ambient temperature.
  • Table 7: life test conditions. This table shows the oven temperature and power applied.

Special remarks

The MMIC lot acceptance specification may be merged with the MMIC procurement specification (see ECSS-Q-60-12 Annex E) on completion of all testing by the manufacturer and user for the finalization of the MMIC detail specification.

ANNEX(normative)MMIC visual inspection summary sheet - DRD

DRD identification

Requirement identification and source document

This DRD is called up from ECSS-Q-ST-60-12, requirement 10.2.4.3c.

Purpose and objective

The purpose of the MMIC visual inspection summary sheet is to summarize the results of the visual inspection performed as part of the wafer acceptance test of the MMIC.

Expected response

Scope and content

The MMIC visual inspection shall include all references for traceability purpose and, as a minimum, the quantities of the following:

  • good dies, sorted after DC and RF testing;
  • rejected dies after visual inspection;
  • accepted dies for each type of MMIC.

Special remarks

None.

ANNEX(informative)References

ESCC QPL, ESA qualified parts list

ESCC/REF 001, List of ESCC documents and specifications under configuration control

CECC 00200, Register of approvals

ISO 14621-1, Space systems Electrical, electronic and electromechanical (EEE) parts Part 1: Parts management

ISO 14621-1, Space systems Electrical, electronic and electromechanical (EEE) parts Part 2: Control programme requirements

Bibliography

ECSS-S-ST-00


ECSS system Description and implementation and general requirements


ESCC 5010


Generic specification for discrete microwave semiconductor components


ESCC 20100


Requirements for qualification of standard electronic components for space application


ESCC 2269010


Evaluation test programme for MMICs